1. Field of Invention
The present invention relates to semiconductor memory devices such as SRAMs (static random access memories).
2. Description of Related Art
SRAMs, one type of semiconductor memory devices, do not require a refreshing operation, and therefore have characteristics that can simplify a system in which they are incorporated and facilitate lower power consumption. For this reason, the SRAMs are prevailingly used as memories for hand-carry type equipment, such as cellular phones.
It is preferable for the hand-carry type equipment to be reduced in size. Therefore, the memory size of the SRAMs must be reduced.
It is an object of the present invention to provide a semiconductor memory device that can reduce the size of memory cells.
In accordance with the present invention, a semiconductor memory device has a memory cell including a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor and a second transfer transistor. The semiconductor device includes a first gate electrode layer and a second gate electrode layer. The first gate electrode layer includes gate electrodes of the first driver transistor and the first load transistor. The second gate electrode layer includes gate electrodes of the second driver transistor and the second load transistor. The first gate electrode layer and the second gate electrode layer have linear patterns, respectively, and are disposed in parallel with each other. Distances between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located and on the side where the driver transistors are located are different from each other.
In accordance with the present invention, distances between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located and on the side where the driver transistors are located are different from each other. Accordingly, in accordance with the present invention, the memory cell region can be effectively utilized. As a result, while the memory cell can be further reduced in size, its characteristics are enhanced such that its power consumption is lowered and its operation is more stabilized. For example, the memory cell region can be effectively utilized in the following manner. The distance between the first gate electrode layer and the second gate electrode layer on the side where the driver transistors are located may be set such that a source contact layer of the driver transistors (where the source contact layer is a conduction layer that is used to connect a source region and a wiring layer) can be disposed inside a gate electrode interlayer region (where the gate electrode interlayer region is a region between the first gate electrode layer and the second gate electrode layer), and the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located may be set to a minimum value on the design rule.
In accordance with the present invention, the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located (for example, 0.2-0.4 xcexcm) may be set to be shorter than the distance between the first gate electrode layer and the second gate electrode layer on the side where the driver transistors are located (for example, 0.41-0.6 xcexcm). The first embodiment of the invention described above includes the feature that distances between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located and on the side where the driver transistors are located are different from each other. In accordance with a second embodiment of the invention, the distance between the first gate electrode layer and the second gate electrode layer on the side where the driver transistors are located (for example, 0.2-0.4 xcexcm) may be shorter than the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located (for example, 0.41-0.6 xcexcm).
The first embodiment may be preferable in the present invention. In an SRAM memory, a current that reads the cells on the order of 100 xcexcA flows through the driver transistors. Therefore, a parasitic resistance in the source regions of the driver transistors needs to be lowered. On the other hand, while the load transistors that function to maintain a cell node high potential side can have a smaller current capacity, an off-leak current needs to be reduced. In accordance with the first embodiment, the distance between the first gate electrode layer and the second gate electrode layer is shorter on the side where the load transistors are located than on the side where the driver transistors are located. Also, the source contact layer on the side of the driver transistors is disposed in the gate electrode interlayer region, and the source contact layer on the side of the load transistors is disposed outside to avoid the gate electrode interlayer region. Therefore, the parasitic resistance at the source sections of the driver transistors can be reduced, such that a higher and more stable operation can be realized. Also, a channel section and an area on the drain-side of the load transistor can be provided with wide regions because the distance between the first gate electrode layer and the second gate electrode layer is short. As a result, the channel length of the load transistor can be made longer than that of the driver transistor. Accordingly, the leak current resulting from the short-channel effect of the load transistor can be reduced. As a result, in accordance with the first embodiment of the present invention, the memory cell region can be effectively utilized, with the result that, while the characteristics are enhanced for lower current consumption and more stable operation, the memory cell can be further miniaturized.
In accordance with the present invention, a source contact layer for the load transistors is located adjacent to end sections of the first and second gate electrode layers on the side of the load transistors. The end sections bend outwardly to avoid contact with the source contact layer for the load transistors. In accordance with the present invention, by outwardly bending the end sections, an area of the gate electrode layer on the outside of the channel region of the load transistors (the source contact side of the load transistors) can be made large. Accordingly, even when there is an alignment error, the gate electrode layer can cover the channel region of the load transistor, whereby an increase in the channel leak current of the load transistors can be prevented. Also, in accordance with the present invention, since the end sections are outwardly bent, the shape of the end sections corrects the light proximity effect. As a result, in accordance with the present embodiment, a proximity effect correction device, such as shelves does not need to be added to the end sections.
In accordance with the present invention, the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located is a minimum value on the design rule.
When the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located is a minimum value on the design rule, the source resistance of the load transistors increases. However, since the load transistor has a small current capacity, its characteristics do not deteriorate. Therefore, in accordance with the present invention, the memory cell can be reduced in size without sacrificing its characteristics.
In accordance with the present invention, load transistors are p-channel type. Generally, p-channel type transistors have a greater short-channel effect (that leads to an increased punch-through current and an increased leak current in the sub-threshold region) than n-channel type transistors. In order to suppress the leak by the short channel effect, the gate length of the p-channel type transistors needs to be longer than the gate length of the n-channel type transistors. In the first embodiment described above, when the load transistors are p-channel type, the load transistors have some extra area on their drain region side even when the gate length of the load transistors is made longer. As a result, the current consumption can be reduced without increasing the memory cell area.
In accordance with the present invention, a source contact layer of the driver transistors is located in a gate electrode interlayer region defined by a region between the first gate electrode layer and the second gate electrode layer. In the first embodiment described above, the distance between the first gate electrode layer and the second gate electrode layer on the side where the driver transistors are located can be made relatively long, and therefore the source contact layer of the driver transistors can be positioned within the gate electrode interlayer region. In this manner, in accordance with the present invention, since the source contact layer of the driver transistors can be positioned within the gate electrode interlayer region, the distance between the channel section of the driver transistors and the source contact layer becomes relatively short, such that the parasitic resistance at the source section can be reduced. At the same time, the source contact layer of the driver transistors is disposed in the center of the memory cell, and does not commonly share the source contact layer with adjacent memory cells. As a result, a current that flows through the source contact layer at the time of a data reading operation is always for one cell, and an operation current of adjacent memory cells does not flow in the source contact layer. As a result, in accordance with the present invention, an increase in the potential on the source terminal, which may be caused by the parasitic resistance in the source section of the driver transistors and the reading current, can be reduced, and therefore high speed operation and stable operation can be realized. Also, since the source contact layer is located in the gate electrode interlayer region, the source contact layer of the driver transistors does not have to be considered in connection to the placement of the word lines, and the word lines can have linear layouts. Accordingly, in accordance with the present invention, the process on the word lines can be facilitated, and deviations in the width dimensions of the word lines (the channel lengths of the transfer transistors) can be reduced. Also, in accordance with the present invention, higher operation speed can be realized because the resistance of the word lines can be reduced.
The present invention further includes first and second drain-drain connection layers and first and second drain-gate connection layers. The gate electrode layers, the drain-drain connection layers and the drain-gate connection layers are located in different layers. In plan view, the first and second gate electrode layers are located between the first drain-drain connection layer and the second drain-drain connection layer. The first drain-drain connection layer connects a drain region of the first driver transistor and a drain region of the first load transistor. The second drain-drain connection layer connects a drain region of the second driver transistor and a drain region of the second load transistor. The first drain-gate connection layer connects the first drain-drain connection layer and the second gate electrode layer. The second drain-gate connection layer connects the second drain-drain connection layer and the first gate electrode layer.
The present invention is equipped with gate electrode layers that become gates of inverters, drain-drain connection layers that connect drains of the inverters, and drain-gate connection layers that connect gates of one of the inverters and drains of the other of the inverters. A semiconductor memory device in accordance with the present invention uses three layers (gate electrode layers, drain-drain connection layers, and drain-gate connection layers) to form flip-flops. Accordingly, patterns in each layer can be simplified (for example, into linear patterns) compared to the case in which flip-flops are formed using two layers. In this manner, in the semiconductor memory device in accordance with the present invention, patterns in each layer can be simplified. As a result, a miniaturized semiconductor memory device with its memory cell size being 4.5 xcexcm2 or smaller, for example, can be manufactured.
Also, in a semiconductor memory device in accordance with the present invention, in plan view, the first and second gate electrode layers are located between the first drain-drain connection layer and the second drain-drain connection layer. Furthermore, a wiring (located in the same layer as the drain-drain connection layer) that connects to the source contact layer can be disposed in the cell central area. As a result, the source contact layer of the driver transistors can be disposed in the central area of the memory cell. Accordingly, the degree of freedom in forming the first and second drain-gate connection layers increases. This is also advantageous with regard to reducing the memory cell size.
In accordance with the present invention, the first and second driver transistors are n-type, the first and second load transistors are p-type, and the first and second transfer transistors are n-type. The invention further includes first, second, third and fourth conduction layers. The first gate electrode layer, the second gate electrode layer and an auxiliary word line are located in the first conduction layer. The first drain-drain connection layer, the second drain-drain connection layer, a power supply line, a first contact pad layer, a second contact pad layer and a third contact pad layer are located in the second conduction layer. The first drain-gate connection layer, the second drain-gate connection layer, a main word line, a fourth contact pad layer, a fifth contact pad layer and a sixth contact pad layer are located in the third conduction layer. A first bit line, a second bit line and a grounding line are located in the fourth conduction layer. The auxiliary word line extends in a first direction. The power supply line connects to source regions of the load transistors. The first contact pad layer is used to connect the first bit line and a source/drain region of the first transfer transistor. The second contact pad layer is used to connect the second bit line and a source/drain region of the second transfer transistor. The third contact pad layer is used to connect source regions of the driver transistors and the grounding line. The main word line extends in the first direction. The fourth contact pad layer is used to connect the first bit line and a source/drain region of the first transfer transistor. The fifth contact pad layer is used to connect the second bit line and a source/drain region of the second transfer transistor. The sixth contact pad layer is used to connect source regions of the driver transistors and the grounding line. The first and second bit lines extend in a second direction which is perpendicular to the first direction.
In accordance with the present invention, a variety of characteristics required for semiconductor memory devices (for example, reduced size, reliability, stability and speed) can be enhanced in a well-balanced manner.
In accordance with the present invention, the first drain-drain connection layer and the second drain-drain connection layer have linear patterns, and the first gate electrode layer, the second gate electrode layer, the first drain-drain connection layer and the second drain-drain connection layer are disposed in parallel with one another. In accordance with the present invention, the patterns are simplified, and therefore semiconductor memory devices having miniaturized memory cells can be manufactured.